Dynamic shift registers are used in computers for a variety of purposes. FIG. 1 shows one well known logic diagram for a dynamic shift register bit. A data bit appears at the input terminal and is blocked by a first data passage control means or transfer gate T1 until T1 senses the next rising edge or next falling edge of a clock pulse CLK1 received thereat. The electric charge associated with the data bit held at T1 is stored in a capacitor such as C1. When T1 allows passage of the data bit (conventionally assumed to be a "0" or a "1"), this bit is logically inverted by a first inverter INV1 and passed to a second bit passage control means or transfer gate T2, which allows passage of the bit only upon receipt thereafter of a rising edge or a falling edge of a second independent clock pulse CLK2. The electric charge associated with the bit held at T2 is stored in a capacitor such as C2; and when T2 releases the bit for passage, the bit is again logically inverted by an inverter INV2 so that the data bit appearing at the output is substantially the same as the data bit appearing at the input. The two clock pulses received from clock pulse sources CLK1 and CLK2 received at bit passage control means T1 and T2, respectively, are drawn from independent clock pulse sequences as shown in FIG. 2, the only constraint being that between any two consecutive pulses of CLK1 a single pulse of CLK2 must appear, and conversely. The clock pulses associated with CLK1 and CLK2 are to be nonoverlapping. The two-phase shift register shown schematically in FIG. 1 has been used throughout the industry for more than twenty years. After one pulse from CLK1 and one pulse from CLK2, the data bit that appeared earlier at the input terminal will appear at the output terminal of this device.
For reference purposes, FIG. 3 shows a common implementation of the two-phase dynamic shift register using n-channel conductivity type MOS transistors T1-T6 for this purpose. Transistors T1 and T4 serve as the transfer gates, TG1 and TG2, respectively, in FIG. 1; transistors T2 and T3 together comprise the inverter INV1; and transistors T5 and T6 together comprise the inverter INV2. Note that each data bit processed requires six transistors and delivery of two clock pulses. One problem that recurs here is that, when a "1" data bit appears at the input terminal in FIG. 3, the bit information transferred from drain (D1) to source (S1) upon subsequent receipt of a clock pulse from clock pulse source CLK1 will not be a true "1" bit because the gate voltage and the source voltage will become substantially equal as the "1" data bit is transferred from drain to source; this will reduce the resulting source-gate voltage difference V.sub.GS1 at transistor T1 to below the threshold V.sub.GS,T (.about.1 volt) for transistor turn-on, thus turning the transistor off, arresting charge build-up, and fixing the voltage for the data bit appearing at the source S1 at a value V.sub.cc -V.sub.GS,T &lt;V.sub.cc. This will reduce the noise margin of the gate voltage V.sub.G2 appearing at the gate G2 of MOS transistor T2 by an amount V.sub.GS,T. A similar difficulty occurs at the transfer gate T4. No such difficulty presents itself in the transfer of a "0" data bit at transfer gate T1 and/or T4 as the voltage difference V.sub.GS1 does not become substantially zero. If the n-channel MOS transistors T1 and T4 in FIG. 3 are replaced by p-channel conductivity type MOS transistors, these p-channel transistors will face an analogous difficulty in transferring a "0" data bit across themselves but will face no such difficulty in transferring a "1" data bit thereacross. In order to provide adequate noise margin for the data bit signals that arrive at the gates G2 and G4 in FIG. 3, increased voltage must be provided, which requires substantial, and often unacceptable, standby power and additional interconnections through the voltage supply V.sub.cc.
FIG. 4 illustrates a common CMOS implementation for a two-phase shift register that has the inherent benefit that it requires no additional standby power. An n-channel CMOS transistor T1 and a p-channel CMOS transistor T2 are connected drain-to-drain and source-to-source as shown, and the gates G1' and G2' of these two transistors receive complementary clock pulses CLK and CLK*. When a "1" data bit appears at the input terminal in FIG. 4, the transfer gate T2' transfers a true "1" irrespective of the value of this data bit transferred by transfer gate T1'; the data bit "1" will, of course, be transferred at different times by the gates T1' and T2'. When a "0" data bit arrives at the input terminal, transfer gate T1' will transfer a true "0" bit irrespective of the reduced value transferred by transfer gate T2', again at slightly different times. The result of this configuration is that the data bit that arrives at the common source S' shown in FIG. 4 is a true " 0" data bit or a true "1" data bit, and no increase in standby power is required to preserve noise margins. A similar result occurs at the combination of transfer gates T5' and T6' shown in FIG. 4.
However, the configuration shown in FIG. 4 requires eight CMOS transistors and delivery of four different clock phase signals and thus requires more semiconductor real estate than the simpler configuration shown in FIG. 3. FIGS. 5 and 6 compare schematically the requirements of the simpler n-channel system indicated in FIG. 3 with the more complex CMOS configuration required by FIG. 4.